A low-swing clock double-edge triggered flip-flop

A low-swing clock double-edge triggered flip-flop (LSDBF) is developed to reduce power consumption significantly compared to conventional FFs. LSDFF avoids unnecessary internal node transition and reduces conflicting currents. The overall power saving in flip-flop operation is estimated to be 30.2 to 50.8% with additional 78% power savings in a clock network.

[1]  F. Klass.  Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[2]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[3]  Young-Su Kwon,et al.  A new single-clock flip-flop for half-swing clocking , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[4]  Satoshi Tanaka,et al.  Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[5]  Duo Sheng,et al.  Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops , 2000, IEEE Journal of Solid-State Circuits.

[6]  Bai-Sun Kong,et al.  Conditional-capture flip-flop technique for statistical power reduction , 2000 .

[7]  Hiroshi Kawaguchi,et al.  A reduced clock-swing flip-flop (RCSFF) for 63% power reduction , 1998, IEEE J. Solid State Circuits.

[8]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[9]  Kawaguchi,et al.  A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction , 1997, Symposium 1997 on VLSI Circuits.

[10]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.