A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3x higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

[1]  Anantha Chandrakasan,et al.  Parallel CABAC for low power video coding , 2008, 2008 15th IEEE International Conference on Image Processing.

[2]  Chun-Chia Chen,et al.  A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[3]  Satoshi Goto,et al.  Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[4]  Chen-Yi Lee,et al.  A novel embedded bandwidth-aware frame compressor for mobile video applications , 2009, 2008 International Symposium on Intelligent Signal Processing and Communications Systems.

[5]  Liang-Gee Chen,et al.  Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control , 2009, 2009 IEEE International Conference on Acoustics, Speech and Signal Processing.

[6]  Liang-Gee Chen,et al.  Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System , 2009, IEEE Transactions on Circuits and Systems for Video Technology.

[7]  Naoto Date,et al.  A rate-controllable near-lossless data compression IP for HDTV decoder LSI in 65nm CMOS , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[8]  Tae Young Lee,et al.  A new frame-recompression algorithm and its hardware design for MPEG-2 video decoders , 2003, IEEE Trans. Circuits Syst. Video Technol..

[9]  Liang-Gee Chen,et al.  A branch selection multi-symbol high throughput CABAC decoder architecture for H.264/AVC , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[10]  Jiun-In Guo,et al.  A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications , 2007, IEEE J. Solid State Circuits.

[11]  Anantha Chandrakasan,et al.  A high throughput CABAC algorithm using syntax element partitioning , 2009, 2009 16th IEEE International Conference on Image Processing (ICIP).

[12]  Satoshi Goto,et al.  A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective , 2009, 2009 Symposium on VLSI Circuits.

[13]  K.K. Parhi,et al.  Parallelization of Context-Based Adaptive Binary Arithmetic Coders , 2006, IEEE Transactions on Signal Processing.

[14]  Madhukar Budagavi,et al.  Video coding using compressed reference frames , 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

[15]  Satoshi Goto,et al.  A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip , 2011, IEEE Journal of Solid-State Circuits.

[16]  Anantha Chandrakasan,et al.  A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder , 2009, IEEE Journal of Solid-State Circuits.

[17]  Y.V. Ivanov,et al.  Reference Frame Compression Using Embedded Reconstruction Patterns for H.264/AVC Decoder , 2008, 2008 The Third International Conference on Digital Telecommunications (icdt 2008).

[18]  Hyuk-Jae Lee,et al.  A New Frame Recompression Algorithm Integrated with H.264 Video Compression , 2007, 2007 IEEE International Symposium on Circuits and Systems.