A High Performance, Low Area Overhead Carry Lookahead Adder

Adders are some of the most critical data path circuits requiring considerable design effort in order to “squeeze” out as much performance gain as possible. Many adder designs manage high performance by reducing the delay of the critical path, an effort that results in high area overhead in most cases. In this paper we present a carry lookahead adder (CLA) with a prediction scheme that results in improved performance and low area overhead. Carry prediction enables for the reduction of the carry circuitry within a block while reducing the delay involved in the generation of the carry-out to the subsequent blocks. We have performed simulations of a 16-bit adder and recorded performance improvements of 67% in propagating the carry and generating the sum when compared with the traditional (fixed group4) CLA designed in the same technology.

[1]  I. Karafyllidis,et al.  Design and simulation of a single-electron full-adder , 2003 .

[2]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[3]  Vojin G. Oklobdzija,et al.  Delay optimization of carry-skip adders and block carry-lookahead adders , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[4]  Chingwei Yeh,et al.  Fast and compact dynamic ripple carry adder design , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[5]  José G. Delgado-Frias,et al.  A hybrid wave pipelined network router , 2002 .

[6]  Lee-Sup Kim,et al.  64-bit carry-select adder with reduced area , 2001 .

[7]  Jabulani Nyathi,et al.  A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[8]  Atila Alvandpour,et al.  A 2.8 ns 30 /spl mu/W/MHz area-efficient 32-b Manchester carry-bypass adder , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[9]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[10]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[11]  Kuo-Hsing Cheng,et al.  A 1.2 V 500 MHz 32-bit carry-lookahead adder , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[12]  Y. Suda,et al.  Novel single-electron logic circuits using charge-induced signal transmission (CIST) structures , 2003 .

[13]  Stefania Perri,et al.  Hybrid carry-select statistical carry look-ahead adder , 1999 .

[14]  Chung-Hsun Huang,et al.  The CMOS carry-forward adders , 2004 .