Automated Range and Precision Bit-Width Allocation for Iterative Computations

As scientific computing becomes more widespread in environments where form-factor considerations necessitate hardware acceleration, the problem of selecting numerical data representations (bit-width allocation), key to accelerator design, is faced with shortcomings in the existing techniques. To address this problem for scientific computing dataflows, we propose a methodology for determining custom hybrid fixed/floating-point data representations for iterative computations.

[1]  Wayne Luk,et al.  Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[2]  Hai Zhou,et al.  Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Wayne Luk,et al.  Wordlength optimization for linear digital signal processing , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  William Cammack,et al.  Fixpt: a C++ method for development of fixed point digital signal processing algorithms , 1994, 1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences.

[5]  Markus Rupp,et al.  Automated floating-point to fixed-point conversion with the fixify environment , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[6]  Alice C. Parker,et al.  Accuracy sensitive word-length selection for algorithm optimization , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[7]  Giovanni De Micheli,et al.  Application of symbolic computer algebra in high-level data-flow synthesis , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Jason Cong,et al.  Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[9]  Katarzyna Radecka,et al.  Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[10]  N. Singla,et al.  Financial Monte Carlo simulation on architecturally diverse systems , 2008, 2008 Workshop on High Performance Computational Finance.

[11]  Yajun Ha,et al.  An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[12]  Patrick Schaumont,et al.  A methodology and design environment for DSP ASIC fixed point refinement , 1999, DATE '99.

[13]  Vasile I. Istrăţescu,et al.  Fixed point theory : an introduction , 1981 .

[14]  Heinrich Meyr,et al.  FRIDGE: a fixed-point design and simulation environment , 1998, Proceedings Design, Automation and Test in Europe.

[15]  De Figueiredo,et al.  Self-validated numerical methods and applications , 1997 .

[16]  James Demmel,et al.  IEEE Standard for Floating-Point Arithmetic , 2008 .

[17]  Wayne Luk,et al.  Unifying bit-width optimisation for fixed-point and floating-point designs , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[18]  Martin Fränzle,et al.  HySAT: An efficient proof engine for bounded model checking of hybrid systems , 2007, Formal Methods Syst. Des..

[19]  Wayne Luk,et al.  Reconfigurable computing: architectures and design methods , 2005 .

[20]  SungWonyong,et al.  Combined word-length optimization and high-level synthesis of digital signal processing systems , 2006 .

[21]  Wayne Luk,et al.  Optimum and heuristic synthesis of multiple word-length architectures , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  M. Altman Review: Vasile I. Istratescu, Fixed point theory: An introduction , 1983 .

[23]  Nicola Nicolici,et al.  Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  J. Shewchuk An Introduction to the Conjugate Gradient Method Without the Agonizing Pain , 1994 .

[25]  Zeljko Zilic,et al.  Arithmetic transforms for compositions of sequential and imprecise datapaths , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Alok N. Choudhary,et al.  Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[27]  Prithviraj Banerjee,et al.  Overview of a compiler for synthesizing MATLAB programs onto FPGAs , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  William E. Higgins,et al.  Combined video tracking and image-video registration for continuous bronchoscopic guidance , 2008, International Journal of Computer Assisted Radiology and Surgery.

[29]  Shahin Sirouspour,et al.  A Parallel Computing Platform for Real-Time Haptic Interaction with Deformable Bodies , 2010, IEEE Transactions on Haptics.

[30]  Kyungtae Han,et al.  Automatic Floating-Point to Fixed-Point Transformations , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[31]  Wayne Luk,et al.  The Multiple Wordlength Paradigm , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[32]  Wonyong Sung,et al.  AUTOSCALER for C: an optimizing floating-point to integer C program converter for fixed-point digital signal processors , 2000 .

[33]  Brian L. Evans,et al.  Wordlength optimization with complexity-and-distortion measure and its application to broadband wireless demodulator design , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[34]  Heinrich Meyr,et al.  System level fixed-point design based on an interpolative approach , 1997, DAC.

[35]  Robert W. Brodersen,et al.  An automated floating-point to fixed-point conversion methodology , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[36]  Nicola Nicolici,et al.  Computational bit-width allocation for operations in vector calculus , 2009, 2009 IEEE International Conference on Computer Design.

[37]  Yvon Savaria,et al.  A comparison of automatic word length optimization procedures , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[38]  Nicola Nicolici,et al.  Robust design methods for hardware accelerators for iterative algorithms in scientific computing , 2010, Design Automation Conference.

[39]  Rob A. Rutenbar,et al.  Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs , 2003, ICCAD 2003.