ESD characterization of high mobility SiGe Quantum Well and Ge devices for future CMOS scaling

The next technology option to keep CMOS scaling on pace after the introduction of finFETs, is the use of High Mobility channels. For the first time, the ESD reliability of such a technology option is studied for pMOS devices using SiGe Quantum Well and Ge channels.

[1]  A. Hikavyy,et al.  Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration , 2011, 2011 International Electron Devices Meeting.

[2]  T. Adam,et al.  Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain , 2006, 2009 Symposium on VLSI Technology.

[3]  Junjun Li,et al.  Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies , 2011, EOS/ESD Symposium Proceedings.

[4]  M. Silberstein,et al.  A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors , 2003, IEEE International Electron Devices Meeting 2003.

[5]  Kah-Wee Ang,et al.  Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors , 2005 .

[6]  T. Vandeweyer,et al.  High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants , 2009, IEEE Electron Device Letters.

[7]  Geert Hellings,et al.  The implant-free quantum well field-effect transistor: Harnessing the power of heterostructures☆ , 2012 .

[8]  Geert Hellings,et al.  Electrical TCAD Simulations of a Germanium pMOSFET Technology , 2010, IEEE Transactions on Electron Devices.

[9]  R. Rooyackers,et al.  Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications , 2008, IEEE Transactions on Electron Devices.

[10]  R. Bolam,et al.  Polarity-dependent oxide breakdown of NFET devices for ultra-thin gate oxide , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[11]  Kwang-Seok Seo,et al.  Performance Evaluation of 50 nm In0.7Ga0.3As HEMTs For Beyond-CMOS Logic Applications , 2005 .

[12]  Marc Heyns,et al.  Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n- and p-FETs on Ge-On-Insulator substrates , 2005 .