A reconfigurable digital signal processor architecture for high-efficiency MPEG-4 video encoding

In this work, the instruction-level and function-level profile analyses of a MPEG-4 video encoder are performed to design a reconfigurable digital signal processor (DSP) architecture. According to the result from the instruction-level profile analysis, the proposed DSP architecture would be lined up with 5 arithmetic logic units (ALUs), 1 multiplier, and 2 load/store units. Such a line-up in the computation units would allow the proposed DSP architecture to have a better parallel processing capability and a higher hardware usage rate in realizing the MPEG-4 video encoder. The result from the function-level profile analysis reveals that the function of motion estimation requires the most computation power. Hence, the proposed DSP architecture reconfigures 4 ALUs and a multiplier to become a functional unit for high parallel processing of motion estimation. This hardware design of motion estimation is primarily dependent on the adders and multiplier of the proposed DSP architecture, plus a few control circuits to convert the computation units. Such arrangement would have less hardware cost than in conventional video processors with specialized functional units for motion estimation. Lastly benchmark analysis and comparison are done between the proposed DSP architecture and TI TMS320C64x architecture. In processing the MPEG-4 video encoder, the proposed DSP architecture is as much as 80% more efficient in computation than the TI TMS320C64x architecture.