High speed multistage CMOS clock buffers with pulse width control loop

In high speed CMOS clock buffer design, the duty cycle of clock is liable to be influenced when the clock passes through a multistage buffer because the circuit is not strictly digital. Signal quality degradation is caused by temperature and process deviation. In this paper, we address a pulse width control loop (PWCL), to get a required pulse width. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulse width can be well controlled if the loop parameters are properly chosen. The pulse width can be easily adjusted to a desired value by changing the ratio of transistor sizes in the current mirror of the charge pump.