Sampling clock jitter effects in digital-to-analog converters

This paper describes sampling clock jitter effects in digital-to-analog converters. A formula for the output error power due to sampling clock jitter for a sinusoidal input is derived and verified by numerical simulations, and its spectrum characteristics is shown. Also its effects on DAC SNR is clarified by numerical simulation as follows: (i) When the total noise power outside as well as inside the signal band is taken into account, the DAC SNR remains almost constant regardless of the sampling jitter. (ii) However, when an analog lowpass filter follows the DAC and only the noise power inside the signal band is considered, the DAC SNR degrades as the jitter increases and the input signal frequency becomes higher. Thus the sampling clock jitter is serious for the high speed DAC.