Fault modeling in controllable polarity silicon nanowire circuits

Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and Fin-FET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals.

[1]  Christian Witt,et al.  Stress control during thermal annealing of copper interconnects , 2011 .

[2]  Wojciech Maly,et al.  CMOS bridging fault detection , 1990, 1991, Proceedings. International Test Conference.

[3]  Edward J. McCluskey,et al.  Three-pattern tests for delay faults , 1994, Proceedings of IEEE VLSI Test Symposium.

[4]  Moo Kit Lee,et al.  IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy , 2007, 16th Asian Test Symposium (ATS 2007).

[5]  G. Micheli,et al.  Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget , 2011 .

[6]  R. Rajsuman,et al.  Iddq testing for CMOS VLSI , 1994, Proceedings of the IEEE.

[7]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[8]  Pascal Gentile,et al.  Multifunctional devices and logic gates with undoped silicon nanowires. , 2012, Nano letters.

[9]  Edward J. McCluskey,et al.  Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Benjamin Bunday,et al.  Measurement of high-k and metal film thickness on FinFET sidewalls using scatterometry , 2008, SPIE Advanced Lithography.

[11]  Víctor H. Champac,et al.  Testing of Stuck-Open Faults in Nanometer Technologies , 2012, IEEE Design & Test of Computers.

[12]  A. N. Bhoj,et al.  Fault Models for Logic Circuits in the Multigate Era , 2012, IEEE Transactions on Nanotechnology.

[13]  Giovanni De Micheli,et al.  An Efficient Gate Library for Ambipolar CNTFET Logic , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Yervant Zorian,et al.  Fault modeling and test algorithm creation strategy for FinFET-based memories , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[15]  N. Singh,et al.  CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing , 2011, IEEE Electron Device Letters.

[16]  Stefan Slesazeck,et al.  Reconfigurable silicon nanowire transistors. , 2012, Nano letters.

[17]  Antonio Rubio,et al.  A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[18]  G. Cohen,et al.  High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[19]  Giovanni De Micheli,et al.  Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[20]  Qiang Xu,et al.  On modeling faults in FinFET logic circuits , 2012, 2012 IEEE International Test Conference.

[21]  Niraj K. Jha,et al.  Fault modeling for FinFET circuits , 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

[22]  Chen-Wei Lin,et al.  Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[23]  J. Knoch,et al.  High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.

[24]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.