HCM: An abstraction layer for seamless programming of DPR FPGA

Well-known for its efficient computing capabilities, FPGA-based architectures also have the potential for high flexibility with dynamic reconfiguration features. Yet, writing applications on these architectures is laborious, poorly portable and hardly scalable to multi-user and/or multi-FPGA systems, mainly because of a mixture of application related code and flexibility management code. In this paper, we propose a new abstraction layer, called Hardware Component Manager (HCM), which clearly separates the allocation of a hardware function from the control of a reconfiguration procedure, and guarantees the security of coexisting configurations. The implementation of this HCM layer on realistic simulation platforms demonstrates its ability to ease the management of FPGA flexibility while preserving performance and ensuring hardware function protection. HCM implementation and its simulation environment are open-source in the hope of reuse by the community.

[1]  Hiroaki Takada,et al.  Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[2]  Dirk Timmermann,et al.  Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[3]  Philippe Coussy,et al.  High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .

[4]  Philippe Coussy,et al.  High-Level Synthesis , 2008 .

[5]  Jürgen Becker,et al.  Dynamic and Partial FPGA Exploitation , 2007, Proceedings of the IEEE.

[6]  Robert W. Brodersen,et al.  Borph: an operating system for fpga-based reconfigurable computers , 2007 .

[7]  Patrick Lysaght,et al.  A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Jari Nurmi,et al.  A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  Marco D. Santambrogio,et al.  Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Ulrich Rückert,et al.  REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[11]  Linda Doyle,et al.  Generic Software Framework for Adaptive Applications on FPGAs , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.