CPU DB

With this open database, you can mine microprocessor trends over the past 40 years.

[1]  Andrew A. Chien,et al.  The future of microprocessors , 2011, Commun. ACM.

[2]  James C. Hoe,et al.  Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[3]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing Technologies , 2010, Proceedings of the IEEE.

[4]  Hsien-Hsin S. Lee,et al.  Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era , 2008, Computer.

[5]  Mark D. Hill,et al.  Amdahl's Law in the Multicore Era , 2008, Computer.

[6]  Shekhar Y. Borkar,et al.  Thousand Core ChipsA Technology Perspective , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[7]  Vijayalakshmi Srinivasan,et al.  Cache miss behavior: is it √2? , 2006, CF '06.

[8]  Thomas R. Puzak,et al.  Optimum power/performance pipeline depth , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[9]  T. Puzak,et al.  The optimum pipeline depth for a microprocessor , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[10]  S. Keckler,et al.  The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[11]  Douglas M. Carmean,et al.  Increasing processor performance by implementing deeper pipelines , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[12]  Edward J. Nowak,et al.  Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..

[13]  V. L. Rideout,et al.  Design of ion-implanted MOSFET's with very small physical dimensions , 1999, IEEE Solid-State Circuits Newsletter.

[14]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.