A new metric for basic-block level rough energy estimation for power-gated VLIW data-path model
暂无分享,去创建一个
Ittetsu Taniguchi | Masahiro Fukui | Kohei Aoki | Hiroyuki Tomiyama | Shunsuke Nakamura | Mitsuya Uchida
[1] Ittetsu Taniguchi,et al. Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors , 2012, 2012 International SoC Design Conference (ISOCC).
[2] Paolo Faraboschi,et al. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools , 2004 .
[3] Francky Catthoor,et al. Playing the trade-off game: Architecture exploration using Coffeee , 2009, TODE.
[4] Y. Kojima,et al. Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating , 2009, 2009 IEEE Asian Solid-State Circuits Conference.
[5] Rudy Lauwereins,et al. Architecture exploration for a reconfigurable architecture template , 2005, IEEE Design & Test of Computers.