Embedded design-for-testability strategies to test high-resolution SD modulators

This paper describes the design-for-testability strategies integrated in a 0.35μm CMOS 17-bit@40-kS/s chopper-stabilized Switched-Capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. After a brief review on the most important effects degrading the circuit performance, a test technique, based on the division of the circuit into several blocks that are tested separately, is presented. Experimental results shows the utility of the implemented test technique to detect errors in the circuit and to characterize the most important blocks with a minimum increase of extra area for the additional test circuitry.