A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application
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[1] Howard C. Luong,et al. 2-V 900-MHz quadrature coupled LC oscillators with improved amplitude and phase matchings , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[2] Behzad Razavi,et al. A 6 GHz 60 mW BiCMOS phase-locked loop with 2 V supply , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[3] M. Bayer,et al. Cell based fully integrated CMOS frequency synthesizers , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
[4] Michiel Steyaert,et al. A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.
[5] Behzad Razavi,et al. RF Microelectronics , 1997 .
[6] W. B. Loh,et al. High quality factor silicon-integrated spiral inductors achieved by using thick top metal with different passivation schemes , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).
[7] K. Halonen,et al. A 4 GHz CMOS multiple modulus prescaler , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[8] B. Razavi,et al. A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology , 2000, IEEE Journal of Solid-State Circuits.
[9] Ali Hajimiri,et al. Phase noise in multi-gigahertz CMOS ring oscillators , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
[10] B. Bisanti,et al. An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with < 10-Hz RF carrier resolution , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[11] M. Steyaert,et al. A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[12] Philip W. Mcentarfer,et al. Cell-based fully integrated CMOS frequency synthesizers , 1993 .
[13] V. Cheung,et al. A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process , 2003, IEEE J. Solid State Circuits.
[14] Byungsoo Chang,et al. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .
[15] H.C. Luong,et al. A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[16] Andrew Z Grzegorek,et al. ∝s Settling and 2Mb/s Closed Loop Modulation , 2000 .
[17] U. Langmann,et al. An 8 GHz silicon bipolar clock-recovery and data-regenerator IC , 1994 .
[18] Jan Craninckx,et al. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .
[19] J. Maligeorgos,et al. A 2 V 5.1-5.8 GHz image-reject receiver with wide dynamic range , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[20] R. Y. Chen. High-speed CMOS frequency divider , 1997 .
[21] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[22] HongMo Wang. A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 /spl mu/m CMOS , 2000 .
[23] H.R. Rategh,et al. A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.
[24] Michiel Steyaert,et al. A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μM CMOS , 1996, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.
[25] Kwyro Lee,et al. A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme , 1997, IEEE J. Solid State Circuits.
[26] M. Wurzer,et al. A 45 GHz SiGe active frequency multiplier , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[27] Kenji Taniguchi,et al. An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[28] Howard C. Luong,et al. A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-/spl mu/m CMOS process , 2002, IMS 2002.
[29] S. S. Rofail,et al. Design and analysis of a ±1V CMOS four-quadrant analogue multiplier , 1998 .
[30] Nikolay Tchamov,et al. 1.2 V gigahertz-resonance-ring ICO/VCO , 1997 .