Hierarchical Graph: A New Cost Effective Architecture for Network on Chip

We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads.

[1]  Robert W. Brodersen,et al.  Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[2]  Gerard J. M. Smit,et al.  A virtual channel router for on-chip networks , 2004, IEEE International SOC Conference, 2004. Proceedings..

[3]  J.D. Day,et al.  The OSI reference model , 1983 .

[4]  Dake Liu,et al.  Network on chip simulations for benchmarking , 2004 .

[5]  Axel Jantsch,et al.  Simulation and Evaluation of a Network on Chip Architecture Using Ns-2 , 2002 .

[6]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[7]  Vu-Duc Ngo,et al.  On chip network: topology design and evaluation using NS2 , 2005, The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005..

[8]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .