A Highly Integrated Joint Servo System Based on FPGA with Nios II Processor

In this paper, FPGA (field programmable gate array) based joint servo system for the HIT/DLR arm has been investigated. A new fully digitized hardware design scheme of a joint servo controller has been presented, which is verified and implemented on one-chip FPGA with embedded NIOS II processor. This scheme not only realizes all sensor data acquisition, SPWM generation and motor vector control, but also realizes joint position, torque control and trajectory generation. Moreover, the realized controller IC also contains a high speed serial (25 Mbps) communication interface based on LVDS (low voltage differential signal), which permits the on-line configuration for all kinds of control parameters. Experimental results demonstrate the effectiveness of the compact joint servo controller for the HIT/DLR arm

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