An Efficient VLSI Architecture and FPGA Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter

Summary This paper presents an efficient VLSI architecture of a high speed, low power 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast lifting scheme approach for (9, 7) filter in DWT, reduces the hardware complexity and memory accesses. Moreover, it has the ability of performing progressive computations by minimizing the buffering between the decomposition levels. The system is fully compatible with JPEG2000 standard. Our designs were realized in VHDL language and optimized in terms of throughput and memory requirements. The implementations are completely parameterized with respect to the size of the input image and the number of decomposition levels. The proposed architecture is verified by simulation and successfully implemented in a Cyclone II and Stratix III FPGAs, and the estimated frequency of operation is 350 MHz. The resulting computing rate is up to 48 frames (4096x2160) per second with 24 bpp. The architecture has regular structure, simple control flow, small embedded buffers and low power consumption. Thus, it is very suitable for new generation image compression systems, such as JPEG2000.

[1]  Sao-Jie Chen,et al.  Design of an efficient VLSI architecture for 2-D discrete wavelet transforms , 1999, IEEE Trans. Consumer Electron..

[2]  I. Daubechies,et al.  Biorthogonal bases of compactly supported wavelets , 1992 .

[3]  Constantinos E. Goutis,et al.  Evaluation of design alternatives for the 2-D-discrete wavelet transform , 2001, IEEE Trans. Circuits Syst. Video Technol..

[4]  Nanning Zheng,et al.  VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder , 2007, IEEE Transactions on Circuits and Systems for Video Technology.

[5]  I. Daubechies,et al.  Wavelet Transforms That Map Integers to Integers , 1998 .

[6]  Seong Mo Park,et al.  An efficient line based VLSI architecture for 2D lifting DWT , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[7]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[8]  M. Omair Ahmad,et al.  A VLSI architecture for a high-speed computation of the 1D discrete wavelet transform , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[9]  Bing-Fei Wu,et al.  A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[10]  John V. McCanny,et al.  Rapid design of biorthogonal wavelet transforms , 2000 .

[11]  Dunshan Yu,et al.  An Efficient VLSI Implementation of Distributed Architecture for DWT , 2006, 2006 IEEE Workshop on Multimedia Signal Processing.

[12]  Liang-Gee Chen,et al.  Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform , 2004, IEEE Transactions on Signal Processing.

[13]  Chaitali Chakrabarti,et al.  A VLSI architecture for lifting-based forward and inverse wavelet transform , 2002, IEEE Trans. Signal Process..

[14]  Kai Liu,et al.  Efficient Line-Based VLSI Architecture for 2-D Lifting DWT , 2006, 2006 International Conference on Image Processing.

[15]  John V. McCanny,et al.  An efficient architecture for the 2-D biorthogonal discrete wavelet transform , 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

[16]  Sergio Bampi,et al.  Area and throughput trade-offs in the design of pipelined discrete wavelet transform architectures , 2005, Design, Automation and Test in Europe.

[17]  Liang-Gee Chen,et al.  An efficient architecture for two-dimensional discrete wavelet transform , 2001, IEEE Trans. Circuits Syst. Video Technol..

[18]  Michael W. Marcellin,et al.  JPEG2000 - image compression fundamentals, standards and practice , 2002, The Kluwer International Series in Engineering and Computer Science.

[19]  Jean-Didier Legat,et al.  Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000 , 2003, IEEE Trans. Circuits Syst. Video Technol..

[20]  Guido Masera,et al.  Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  W. Sweldens.  The Lifting Scheme: A Custom - Design Construction of Biorthogonal Wavelets "Industrial Mathematics , 1996 .

[22]  Wei Li,et al.  A VLSI architecture for discrete wavelet transform , 1996, Proceedings of 3rd IEEE International Conference on Image Processing.