DESIGN METHODOLOGY FOR mGH-SPEED ITERATIVE DECODER ARCmTECTURES

We propose a novel approach to the design and analysis of VLSI architectures for the soft-input soft-output a posteri­ ori probability (SISO-APP) decoding algorithm used in it­ erative decoders such as turbo decoders. The approach is based on a tile-graph composed of recursion patterns that model the resource-time scheduling of the forward-backward recursion equations of the algorithm. The problem of con­ structing a SISO-APP architecture is formulated as a three­ step process of constructing and counting the patterns needed and then tiling them. The problem of optimizing the archi­ tecture for high speed and low power reduces to optimizing the individual patterns and the tiling scheme for minimal de­ lay and storage overhead. The various forms of the sliding and parallel-window (PW) architectures in the literature are instances of the proposed tile-graph. Using the ti le-graph approach, a new PW architecture controlled by the window width r is proposed that achieves for r = 10 a 45%, a 71%, a 51%, and a 25% reduction in decoding delay, state, in­ put, and output metries storage respectively, compared to a conventional architecture with a 10% increase in resources.