论文信息 - 3D TSV processes and its assembly/packaging technology

3D TSV processes and its assembly/packaging technology

Demand for Through Silicon Via (TSV) is being driven by the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies.

[1] Miko Elwenspoek,et al. High resolution powder blast micromachining , 2000, Proceedings IEEE Thirteenth Annual International Conference on Micro Electro Mechanical Systems (Cat. No.00CH36308).

[2] Bo Tan,et al. Deep micro hole drilling in a silicon substrate using multi-bursts of nanosecond UV laser pulses , 2005 .

[3] Keith A. Jenkins,et al. Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..

[4] S. Nathapong,et al. Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging , 2008, 2008 10th Electronics Packaging Technology Conference.

[5] Pasqualina M. Sarro,et al. Temperature influence on etching deep holes with SF6/O2 cryogenic plasma , 2002 .

[6] Lesley Anne Polka. Package Technology to Address the Memory Bandwidth Challenge for Terascale Computing , 2007 .