A Transition Isolation Scan Cell Design for Low Shift and Capture Power

Shift and capture power management has become indispensable for modern complex low-power designs. Excessive shift power increases test application time and may jeopardize the shift operation correctness, excessive capture power during at-speed scan testing may lead to yield loss. This paper proposes a scan cell design which isolates scan cells output transitions in both shift and capture modes. Experimental results on larger ISCAS'89, ITC'99, and IWLS'05 benchmark circuits show that the proposed scan cell design lowers capture power consumptions with reasonable CPU times and test set inflation.

[1]  V. Kamakoti,et al.  Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[2]  Vinay Jayaram,et al.  Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[3]  Chien-Mo James Li,et al.  Jump scan: a DFT technique for low power testing , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[4]  S. Pravossoudovitch,et al.  A gated clock scheme for low power scan testing of logic ICs or embedded cores , 2001, Proceedings 10th Asian Test Symposium.

[5]  Kohei Miyase,et al.  XID: Don't care identification of test patterns for combinational circuits , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Nur A. Touba,et al.  Inserting test points to control peak power during scan testing , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[7]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[8]  Xiaoqing Wen,et al.  A novel scan segmentation design method for avoiding shift timing failure in scan testing , 2011, 2011 IEEE International Test Conference.

[9]  Srivaths Ravi,et al.  Power-aware test: Challenges and solutions , 2007, 2007 IEEE International Test Conference.

[10]  Xiaoqing Wen,et al.  Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Takaki Yoshida,et al.  MD-SCAN method for low power scan testing , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[12]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Wu-Tung Cheng,et al.  A scalable quantitative measure of IR-drop effects for scan pattern generation , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[14]  Xiaoqing Wen,et al.  A novel scheme to reduce power supply noise for high-quality at-speed scan testing , 2007, 2007 IEEE International Test Conference.

[15]  Kozo Kinoshita,et al.  A new ATPG method for efficient capture power reduction during scan testing , 2006, 24th IEEE VLSI Test Symposium.

[16]  C. P. Ravikumar,et al.  A critical-path-aware partial gating approach for test power reduction , 2007, TODE.

[17]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[18]  Aiman H. El-Maleh,et al.  An efficient test relaxation technique for synchronous sequential circuits , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Wenlong Wei,et al.  A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture , 2007, 2007 Asia and South Pacific Design Automation Conference.

[20]  Patrick Girard,et al.  A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[21]  Bashir M. Al-Hashimi,et al.  Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Irith Pomeranz,et al.  On reducing peak current and power during test , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[23]  Kozo Kinoshita,et al.  Low-capture-power test generation for scan-based at-speed testing , 2005, IEEE International Conference on Test, 2005..

[24]  Wei Zhao,et al.  Power-safe test application using an effective gating approach considering current limits , 2011, 29th VLSI Test Symposium.

[25]  Wu-Tung Cheng,et al.  Improved weight assignment for logic switching activity during at-speed test pattern generation , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[26]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.