The design and verification of a high-performance low-control-overhead asynchronous differential equation solver

This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable synchronous design (designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.

[1]  Bruce E. Briley Some New Results on Average Worst Case Carry , 1973, IEEE Transactions on Computers.

[2]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[3]  Alain J. Martin Programming in VLSI: from communicating processes to delay-insensitive circuits , 1991 .

[4]  Mark Horowitz,et al.  A zero-overhead self-timed 160-ns 54-b CMOS divider , 1991 .

[5]  J. Burch Trace algebra for automatic verification of real-time concurrent systems , 1992 .

[6]  Jim D. Garside A CMOS VLSI Implementation of an Asynchronous ALU , 1993, Asynchronous Design Methodologies.

[7]  A. Albicki,et al.  Self-timed adder with pipelined output , 1993, Proceedings of 36th Midwest Symposium on Circuits and Systems.

[8]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[9]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[10]  David L. Dill,et al.  Synthesis of Asynchronous Controllers for Heterogeneous Systems , 1994 .

[11]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[12]  Thomas A. Henzinger,et al.  Symbolic Model Checking for Real-Time Systems , 1994, Inf. Comput..

[13]  Steve Furber Computing without Clocks: Micropipelining the ARM Processor , 1995 .

[14]  David Kinniment An evaluation of asynchronous addition , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[16]  C. Lemonds A high throughput 16 by 16 bit multiplier for DSP cores , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[17]  Kenneth Y. Yun Automatic synthesis of extended burst-mode circuits using generalized C-elements , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[18]  Ganesh Gopalakrishnan,et al.  A technique for synthesizing distributed burst-mode circuits , 1996, DAC '96.

[19]  Peter A. Beerel,et al.  RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking , 1997, Integr..

[20]  Kenneth Y. Yun,et al.  Timing analysis for extended burst-mode circuits , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[21]  Peter A. Beerel,et al.  Speculative completion for the design of high-performance asynchronous dynamic adders , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[22]  Jim D. Garside,et al.  AMULET1: A Asynchronous ARM Microprocessor , 1997, IEEE Trans. Computers.

[23]  David L. Dill,et al.  Practical timing analysis of asynchronous circuits using time separation of events , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).