Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

In this paper, a unique adaptive layout methodology for accurate interconnection between two or more functional chips at the wafer level is presented. The methodology is based on an automatic layout modification for each embedded chip with considering exact related offset and rotation after chip embedding. As a result, a wafer-level embedding and accurate interconnecting and integrating of ultrathin chips in the polymer are feasible. The significant application of the presented accurate interconnection between the groups of functional chips is the microhybrid system-in-foil. Also, an adaptive interconnect layout at wafer-level base, allowing for a small wire pitch on and off the chip, leads to reducing silicon area and, thus, saves cost. In this paper, the process flow for embedding and integrating chips based on the adaptive layout technique is presented. The custom designed test chips are processed for the measurement and optimization of overlay accuracy of the adaptive interconnect layout regardless of the chip thickness, warpage, and topography. Besides, the electrical measurements after integrating ultrathin chips in foil confirm the interconnection between chips.