Robustsless Enhancement And Detection Threshold Reduction In ATPG For Gate Delay Faults

In this paper, we introduce a new test generation algorithm for testing ate delay fault. The main new feature of the algoritfm is that it uses auantitanve information about detection threshold Fd robustness to guide its choice of the fault sensitizabon path and the associated line j-ustifications. The. algorithm attempts. to reduce the detectnon threshold and increase the quanbtabve robustness of the test s. Thus, with this new algorithm, we are able to show Etest pattern sets generated by the algorithm achieve better fault coverage, detection threshold and robustness than those that are generated randomly.

[1]  Weiwei Mao.  Fault simulation, test generation and design for testability to detect delay faults in digital circuits , 1992 .

[2]  Michael D. Ciletti,et al.  A variable observation time method for testing delay faults , 1991, DAC '90.

[3]  T. Hayashi,et al.  A Delay Test System for High Speed Logic LSI's , 1986, DAC 1986.

[4]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[5]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[6]  M. Ray Mercer,et al.  A Deterministic Approach to Adjacency Testing for Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[7]  Yashwant K. Malaiya,et al.  Test generation for delay faults using stuck-at-fault test set , 1980 .

[8]  Michael D. Ciletti,et al.  A Simplified Six-Waveform Type Method for Delay Fault Testing , 1989, 26th ACM/IEEE Design Automation Conference.

[9]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[10]  M. Ray Mercer,et al.  A method of delay fault test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[11]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[12]  Michael D. Ciletti,et al.  A quantitative measure of robustness for delay fault testing , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[13]  M. Ray Mercer,et al.  An efficient delay test generation system for combinational logic circuits , 1991, DAC '90.

[14]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[16]  Barry K. Rosen,et al.  Delay test generation. II. Algebra and algorithms , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[17]  Sudhakar M. Reddy,et al.  On the computation of the ranges of detected delay fault sizes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[18]  Yashwant K. Malaiya,et al.  Modeling and Testing for Timing Faults in Synchronous Sequential Circuits , 1984, IEEE Design & Test of Computers.