A radiation-hardened low-power pipelined SAR ADC for CZT-based imaging system

A 12-bit 2M Samples/s pipelined SAR ADC for CZT-based imaging system is presented. It pipelines a first stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second stage 8-bit SAR ADC. The inter-stage gain of 16 instead of 64 is implemented in the 6-bit SAR-based MDAC for minimizing the power dissipation. The second stage 8-bit SAR ADC uses a split-capacitor architecture for reducing the load capacitance of the residue amplifier and then the power dissipation is minimized. In addition, several radiation-hardened-by-design technologies are adopted at layout design for improving pipelined SAR ADC's radiation tolerance. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and occupies a core area of 700μm × 1018 μm. The proposed pipelined SAR ADC achieves 63.7 dB SNDR at 2M Samples/s sampling rate and consumes 12 mW power. The FOM of the proposed ADC is 4.76pJ/conversion-step.

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