a Dsp Engine for a 64-ELEMENT Array

This paper considers the feasibility of software-defined signal processing for a 64-element antenna array. In the proposed architecture, the signal from each element of the array is individually converted to a digital complex baseband format. These 64 outputs are then distributed among many DSP microprocessors, which take turns acquiring and processing the data. The processing is done entirely in software; no FPGAs or ASICs are used. The advantage of software implementation is the ability to dynamically and flexibly allocate the available computing resources to various tasks. Also, the architecture is flat as opposed to hierarchical; every DSP receives data from all antennas. A limited test of this approach using C language source code and commercial off-the-shelf hardware was conducted using the ADSP-21060 “SHARC” DSP. The following processing algorithm was considered as a test of the architecture: In-line calibration, 2D-FFT to form 64 beams, and then 64 length-256 1D-FFTs to obtain the frequency spectrum for each beam. The resulting performance equation is FS (duty cycle) c1J , where FS is the sample rate, c1 = 2:34 10 samples/s, and J is the number of modular computing “clusters” used in the design. This study suggests that c1 can be improved by one or two orders of magnitude using the existing hardware.