Controller for instruction cache and instruction translation look-aside buffer, and method of controlling the same

A controller, and a control method of the instruction cache and instruction translation lookaside buffer is provided. The instruction cache and instruction translation lookaside buffer of the controller (instruction TLB) comprises a processor core, branch predictors, branch target buffer, and the address selection unit. A branch predictor to output a final branch prediction value by performing a branch prediction address for the current command outputted from the processor core. The branch target buffer at the same time the branch prediction by the branch predictor predicts the branch target address of the address for the current command outputted from the processor core, and outputs the predicted target address. An address selection unit and outputs the selected one of the address and a predicted target address of the current instruction is a result of the branch prediction non Taken. Branch prediction and branch target address predicted for the address of the current instruction is immediately prior instruction of the current instruction is started before the branch prediction and branch target address predicted for the address of the previous instruction ends under not a branch instruction assumed, from the address selection unit address output is the cache line corresponding to the instruction cache and the instruction TLB using the dynamic voltage scaling wake-up is. A controller, and a control method of the instruction cache and the instruction TLB will wake the instruction cache and the instruction TLB using a Dynamic Voltage Scaling-up can be prevented penalty.