A design strategy for low-voltage low-power continuous-time /spl Sigma//spl Delta/ A/D converters

This paper presents a design strategy for low-voltage low-power /spl Sigma//spl Delta/ analog-to-digital (A/D) converter using a continuous-time (CT) lowpass loop filter. An improved method is used to find the optimal /spl Sigma//spl Delta/ modulator implementation with respect to a minimal power consumption on the one hand and to fulfil a rapid prototyping approach on the other hand. The influence of the low supply voltage as well as circuit nonidealities on the overall /spl Sigma//spl Delta/ modulator is determined and verified by behavioral simulations. Transistor-level simulation results of a 1.5 V CT /spl Sigma//spl Delta/ A/D converter show a 75 dB dynamic range in a bandwidth of 25 kHz.