A 12b 11MS/s successive approximation ADC with two comparators in 0.13μm CMOS

A two-comparator architecture, incorporating deliberate comparator offset and pre-amplifier power management, reduces comparator meta-stability and comparator power consumption in a 12b 11MS/s SAR ADC. A prototype, fabricated in 0.13μm CMOS achieves an FOM, SNDR, SFDR and error rate of 311fJ/conversion step, 62.4dB and 72.8dB and ≪1.9×10−12, respectively, at 11MS/s.

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