Data path construction and refinement

A system is described for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The actions taken in each phase are described. The authors' contributions include the following: (1) theorems for the lower bound of the number of interconnections; (2) in the DPR phase, a more global view of the allocation problem is taken by ripping up and reallocating different types of objects simultaneously; (3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; (4) a method to judge the potential for upgrading a data path; and (5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results.<<ETX>>

[1]  Yu-Chin Hsu,et al.  Data path allocation based on bipartite weighted matching , 1990, 27th ACM/IEEE Design Automation Conference.

[2]  Srinivas Devadas,et al.  Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Donald E. Thomas,et al.  Automatic Data Path Synthesis , 1983, Computer.

[4]  P. Six,et al.  Cathedral-II: A Silicon Compiler for Digital Signal Processing , 1986, IEEE Design & Test of Computers.

[5]  Pierre G. Paulin,et al.  Scheduling and Binding Algorithms for High-Level Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.

[6]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Donald E. Thomas,et al.  The system architect's workbench , 1988, DAC '88.

[8]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Mohamed I. Elmasry,et al.  Architectural synthesis for DSP silicon compilers , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Barry M. Pangrle Splicer: a heuristic approach to connectivity binding , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[11]  Alice C. Parker,et al.  MAHA: A Program for Datapath Synthesis , 1986, DAC 1986.

[12]  Rajiv Jain,et al.  Experience with the ADAM Synthesis System , 1989, 26th ACM/IEEE Design Automation Conference.