System-Level Modeling ofaNoC-Based H.264Decoder

Networks-on-chip (NoC) areexpected toplaya extend theapplicability oftheMoore's law,dependupon keyroleinfuture embedded systems. A NoC-based system has concurrency and synchronization in bothsoftware and thepotential tosupport concurrent processing, inbothsoftwarehardware toachieve thatgoal. Concurrency issues, ifignored, andhardware. Thiscanhowever leadtoconcurrency issues. We mayalsoleadthesystem intoadeadlock oralivelock state. present a multiprocessor systemmodeling andperformanceTraditional systemdesignintegration and verification evaluation approach thataddresses concurrency. We illustrate ourmethodology bymapping aH.264decoder ontoa4x3mesh- aroaches will not becost-effective inexposig concurrency basedNoCarchitecture. We showlatency, area, andpower failures as theseareintermittent: suchfailures can consumption results forthis NoCarchitecture abstracted fromits significantly increase time-to-market andfield failures. To FPGAimplementation. overcome suchfailures, onewouldhavetodevelop abstract concurrency modelsanddoexhaustive analysis onthese