Within-die gate delay variability measurement using re-configurable ring oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65 nm process node show the feasibility of measuring the delay of an individual inverter to within 1 pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

[1]  Manjul Bhushan,et al.  Product-representative 'at speed' test structures for CMOS characterization , 2006, IBM J. Res. Dev..

[2]  J.A. Kash,et al.  Picosecond imaging circuit analysis of the POWER3 clock distribution , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[3]  M.B. Ketchen,et al.  Ring oscillators for CMOS process tuning and variability control , 2006, IEEE Transactions on Semiconductor Manufacturing.

[4]  Alessandro Bogliolo,et al.  Random sampling for on-chip characterization of standard-cell propagation delay , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[5]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[6]  David Blaauw,et al.  Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Chenming Hu,et al.  Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction , 2004, IEEE Transactions on Semiconductor Manufacturing.

[8]  P. Fisher,et al.  Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices? , 2004, IEEE Transactions on Semiconductor Manufacturing.

[9]  Y. Sonobe,et al.  Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics , 2004, IEEE Transactions on Electron Devices.

[10]  Ashish Jain,et al.  An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[11]  Alessandro Bogliolo,et al.  Measuring the effects of process variations on circuit performance by means of digitally-controllable ring oscillators , 2003, International Conference on Microelectronic Test Structures, 2003..

[12]  Gordon W. Roberts,et al.  Circuits for on-chip sub-nanosecond signal capture and characterization , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[13]  Hidetoshi Onodera,et al.  A Statistical Gate-Delay Model Considering Intra-Gate Variability , 2003, ICCAD 2003.

[14]  A. Asenov,et al.  Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[15]  Sani R. Nassif,et al.  Test structures for delay variability , 2002, TAU '02.

[16]  H. Masuda,et al.  Analysis and characterization of device variations in an LSI chip using an integrated device matrix array , 2003, IEEE Transactions on Semiconductor Manufacturing.

[17]  Steven Kasapi,et al.  Practical, non-invasive optical probing for flip-chip devices , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[18]  Atsushi Kurokawa,et al.  Challenge: variability characterization and modeling for 65- to 90-nm processes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[19]  Duane S. Boning,et al.  The care and feeding of your statistical static timer , 2004, ICCAD 2004.

[20]  Kaushik Roy,et al.  Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[21]  Joseph Sinohin Panganiban.  A ring oscillator based variation test chip , 2002 .

[22]  Bo Zhou,et al.  Measurement of delay mismatch due to process variations by means of modified ring oscillators , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[23]  Anantha Chandrakasan,et al.  A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).