Advancing supercomputer performance through interconnection topology synthesis

In today's many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow to discover the best topology in terms of the communication latency and physical constraints. First a set of representative candidate topologies are generated for the interconnection networks among computing chips; then an efficient multi-commodity flow algorithm is devised to evaluate the performance. The experiments show that the best topologies identified by our algorithm can achieve better average latency compared to the existing networks.

[1]  William J. Dally.  Interconnect-Centric Computing , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[2]  Yi Zhu,et al.  Communication latency aware low power NoC synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[3]  Gerard V. Kopcsay,et al.  Packaging the Blue Gene/L supercomputer , 2005, IBM J. Res. Dev..

[4]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[5]  George L.-T. Chiu,et al.  Overview of the Blue Gene/L system architecture , 2005, IBM J. Res. Dev..

[6]  George Karakostas.  Faster approximation schemes for fractional multicommodity flow problems , 2002, SODA '02.

[7]  David H. Bailey,et al.  The Nas Parallel Benchmarks , 1991, Int. J. High Perform. Comput. Appl..

[8]  Philip Heidelberger,et al.  Optimizing task layout on the Blue Gene/L supercomputer , 2005, IBM J. Res. Dev..

[9]  William J. Dally,et al.  A Delay Model for Router Microarchitectures , 2001, IEEE Micro.

[10]  Andrew A. Chien,et al.  Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization , 2005, 2005 International Conference on Computer Design.