Instruction Cache Design for Energy-Aware Embedded Processors by Using Backward Branch Information

Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful embedded processors. Unfortunately, as the computing power of a processor increases, energy consumption in the processor dramatically increases. For this reason, energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in a embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Analysis results show that the proposed cache reduces the energy consumption by 20% on the average, compared to the traditional cache.

[1]  Moon Ho Lee,et al.  A new reverse jacket transform and its fast algorithm , 2000 .

[2]  Emmett Witchel.  The Span Cache: Software Controlled Tag Checks and Cache Line Size , 2001 .

[3]  Albert Ma,et al.  Way Memoization to Reduce Fetch Energy in Instruction Caches , 2001 .

[4]  Sergey Brin,et al.  The Anatomy of a Large-Scale Hypertextual Web Search Engine , 1998, Comput. Networks.

[5]  Kaushik Roy,et al.  Reducing set-associative cache energy via way-prediction and selective direct-mapping , 2001, MICRO.

[6]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .

[7]  Cheol Hong Kim,et al.  An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors , 2006, IEICE Trans. Inf. Syst..

[8]  B. Sundar Rajan,et al.  A generalized reverse jacket transform , 2001 .

[9]  Debajyoti Mukhopadhyay,et al.  An approach to confidence based page ranking for user oriented Web search , 2003, SGMD.

[10]  Sriram Raghavan,et al.  Searching the Web , 2001, ACM Trans. Internet Techn..

[11]  Kaushik Roy,et al.  Reducing set-associative cache energy via way-prediction and selective direct-mapping , 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

[12]  Debajyoti Mukhopadhyay,et al.  FlexiRank: An Algorithm Offering Flexibility and Accuracy for Ranking the Web Pages , 2005, ICDCIT.

[13]  Debajyoti Mukhopadhyay,et al.  An Alternate Way to Rank Hyper-linked Web-Pages , 2006, 9th International Conference on Information Technology (ICIT'06).

[14]  John Arends,et al.  Instruction fetch energy reduction using loop caches for embedded applications with small tight loops , 1999, ISLPED '99.

[15]  Simon Segars.  Low power design techniques for microprocessors , 2000 .

[16]  Norman P. Jouppi,et al.  Cacti 3. 0: an integrated cache timing, power, and area model , 2001 .

[17]  Kanad Ghose,et al.  Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[18]  Kazuaki Murakami,et al.  A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection , 2000 .

[19]  Santanu Chattopadhyay,et al.  Additive cellular automata : theory and applications , 1997 .

[20]  Debajyoti Mukhopadhyay,et al.  Generation of SMACA and Its Application in Web Services , 2007, PaCT.

[21]  Kanad Ghose,et al.  Analytical energy dissipation models for low-power caches , 1997, ISLPED '97.

[22]  William H. Mangione-Smith,et al.  The filter cache: an energy efficient memory structure , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.