A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages

A new contention-free domino logic (CF-Domino) that is especially suited for low threshold voltage (LVT) is reported. Its superior noise margin and speed over conventional domino circuits for LVTs are demonstrated using HSPICE(R) simulations and a 0.25 /spl mu/m CMOS technology with a supply voltage of 2.5 V. The impacts of the new technique on dynamic and leakage powers and area are also presented.

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