An integrated IDEF0-3/CTPN/SFC approach for design and analysis of discrete event control systems

Due to its low cost and increased reliability, the programmable logical controller (PLC) plays an important role in industry automation. However, as systems become larger and more complex, efficient and systematic analysis and design of PLCs become a more important issue. In this research, an integrated IDEF0-3/CTPN/SFC (IPS) for developing discrete event control systems (DECSs) is presented. The proposed integrated methodology provides a complete and systematic development process for the DECSs. The development process is divided into four stages: functional analysis, system behaviour analysis, system design, and system implementation. The IDEF0-3, coloured timed Petri net (CTPN) and sequential function chart (SFC) are integrated into the corresponding stages based on their characteristics. In addition, the transformation rules between the IDEF0-3 and CTPN and between CTPN and SFC are also conducted for developing DECSs. The transformation rules provide a straightforward mapping from the IDEF0-3 to CTPN and from the CTPN to SFC. The result of the integrated IPS systematically leads to SFC for PLC implementation. Finally, a ball assorting system is given to illustrate how the integrated IPS approach is implemented for developing the DECSs.

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