Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

[1]  Snorre Aunet.  Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS , 2002 .

[2]  Gloria Huertas,et al.  A practical floating-gate Muller-C element using vMOS threshold gates , 2001 .

[3]  S. Aunet,et al.  Ultra low power fault tolerant neural inspired CMOS logic , 2005, Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005..

[4]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[5]  Snorre Aunet,et al.  Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold , 2005 .

[6]  A.J. Lopez-Martin,et al.  Very low-voltage analog signal processing based on quasi-floating gate transistors , 2004, IEEE Journal of Solid-State Circuits.

[7]  Trond Ytterdal,et al.  A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[8]  Mircea R. Stan.  Low-power CMOS with subvolt supply voltages , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[9]  C. Diorio,et al.  A simulation model for floating-gate MOS synapse transistors , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  Tor Sverre Lande,et al.  Overview of floating-gate devices, circuits, and systems , 2001 .

[11]  Siegfried Selberherr,et al.  Ultra-low-power CMOS technologies , 1996, 1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings.