Single-event upset in commercial silicon-on-insulator PowerPC microprocessors

Single-event upset effects from heavy ions and protons are measured for Motorola and IBM silicon-on-insulator (SOT) microprocessors, and compared with results for similar devices with bulk substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collection depth is more than an order of magnitude smaller in the SOI devices.

[1]  O. Musseau Single-event effects in SOI technologies and devices , 1996 .

[2]  D. Schepis,et al.  Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies , 1997 .

[3]  David J. Frank,et al.  Nanoscale CMOS , 1999, Proc. IEEE.

[4]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[5]  T. Iwamatsu,et al.  Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  S. Narasimha,et al.  A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[7]  J. Colinge Silicon-on-Insulator Technology , 1991 .

[8]  Farokh Irom,et al.  Single-event upset in the PowerPC750 microprocessor , 2001 .

[9]  D. M. Hiemstra,et al.  Single event upset characterization of the Pentium(R) MMX and Pentium(R) II microprocessors using proton irradiation , 1999 .

[10]  T. Chapuis,et al.  Seu And Latch-up Results For Sparc Processors , 1993, 1993 IEEE Radiation Effects Data Workshop.

[11]  R. Koga,et al.  Techniques of Microprocessor Testing and SEU-Rate Prediction , 1985, IEEE Transactions on Nuclear Science.

[12]  Hyungsoon Shin Modeling of alpha-particle-induced soft error rate in DRAM , 1999 .