Wave propagation based analytical model for distributed on-chip RLC interconnects
暂无分享,去创建一个
[1] Andrew B. Kahng,et al. An Analytical Delay Model for Interconnects , 1997 .
[2] D. Kramer,et al. A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[3] Lawrence T. Pileggi,et al. Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Jacob K. White,et al. Layout techniques for minimizing on-chip interconnect self-inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[5] S. Wong,et al. On-chip inductance modeling of VLSI interconnects , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[6] P. Roper,et al. Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[7] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[8] Mark Horowitz,et al. Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] H. J. Kadim,et al. Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[10] Kaustav Banerjee,et al. Analysis of on-chip inductance effects for distributed RLC interconnects , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[12] Mattan Kamon,et al. FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .
[13] Keith A. Jenkins,et al. When are transmission-line effects important for on-chip interconnections? , 1997 .
[14] Lawrence T. Pileggi,et al. PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.
[15] L.M. Coulibaly,et al. Analytical ramp delay model for distributed on-chip RLC interconnects , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..
[16] L.M. Coulibaly,et al. A Comparative Analysis of a Distributed On-Chip RLC Interconnect Model under Ramp Excitation , 2005, EUROCON 2005 - The International Conference on "Computer as a Tool".
[17] Lawrence T. Pileggi,et al. The Elmore delay as a bound for RC trees with generalized input signals , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[19] Yehea I. Ismail,et al. Equivalent Elmore delay for RLC trees , 1999, DAC '99.