A Resistorless Small Area, Low Power Cmos Four-quadrant Multiplier

A small area, low power CMOS four-quadrant multiplier is proposed. It is based on a Linear Differential AmplifieraDA), a multiplier core and a fully differential folded cascode(FC) output stage. The conventional resistor load implementation is avoided by converting a fully differential output current of the multiplier core into a fully differential voltage signal by a folded cascode transresistance amplifier. This configuration not only improves the linearity but also occupies small area. The test CMOS-chip is functional and only consumes 36OpW for a f3V power supply. The total silicon area is only 0.07mm2. The input voltage range is a function of the bias current. Experimental results show less than 1 % linearity error for k l V input.

[1]  Edgar Sánchez-Sinencio,et al.  A general purpose discrete-time multiplexing neuron-array architecture , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[2]  Z. Wang,et al.  A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance , 1991 .

[3]  Jaime Ramírez-Angulo.  Highly Linear Four Quadrant Analog BiCMOS Multiplier for ± 1.5 V Supply Operation , 1993, ISCAS.

[4]  J.S. Pena-Finol,et al.  A MOS four-quadrant analog multiplier using the quarter-square technique , 1987 .

[5]  Cheng-Chieh Chang,et al.  CMOS subthreshold four-quadrant multiplier based on unbalanced source-coupled pairs , 1995 .

[6]  K. Bult,et al.  A CMOS Four-Quadrant Analog Multiplier , 1986 .

[7]  Ho-Jun Song,et al.  An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers , 1990 .

[8]  A.L. Coban,et al.  A 1.5 V four-quadrant analog multiplier , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[9]  Ashok Nedungadi,et al.  Design of linear CMOS transconductance elements , 1984 .

[10]  Joseph H. Nevin,et al.  Design procedures for a fully differential folded-cascode CMOS operational amplifier , 1989 .

[11]  K. Kimura,et al.  An MOS four-quadrant analog multiplier based on the multitail technique using a quadritail cell as a multiplier core , 1995 .

[12]  Randall L. Geiger,et al.  VLSI Design Techniques for Analog and Digital Circuits , 1989 .

[13]  Randall L. Geiger,et al.  A ?5-V CMOS analog multiplier , 1987 .

[14]  C.A.T. Salama,et al.  Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages , 1986 .

[15]  Z. Wang.  A four-transistor four-quadrant analog multiplier using MOS transistors operating in the saturation region , 1993 .

[16]  Edgar Sánchez-Sinencio,et al.  Linearity, accuracy and bandwidth considerations in wideband CMOS voltage amplifiers , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[17]  Joseph H. Nevin,et al.  A fully integrated all-enhancement PMOS four-quadrant analogue multiplier , 1986 .

[18]  Francois Krummenacher,et al.  A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.