Computer aided two-dimensional analysis of the junction field-effect transistor

A two-dimensional analysis is presented of the mechanisms of operation for a junction field-effect transistor. Particular emphasis is placed upon the process of electric current saturation in both wide gate and narrow gate structures. It is shown that velocity saturated carrier transport in a source-drain channel produces heretofore unreported mechanisms of device operation. Comparisons made between the conclusions derived from this two-dimensional analysis and the conventional one-dimensional theory of JFET operation are presented in graphic form.

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