NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning

ing with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2020 Association for Computing Machinery. 1084-4309/2020/08-ART41 $15.00 https://doi.org/10.1145/3388141 ACM Transactions on Design Automation of Electronic Systems, Vol. 25, No. 5, Article 41. Pub. date: August 2020. 41:2 Y. Nasser et al. ACM Reference format: Yehya Nasser, Carlo Sau, Jean-Christophe Prévotet, Tiziana Fanni, Francesca Palumbo, Maryline Hélard, and Luigi Raffo. 2020. NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning. ACM Trans. Des. Autom. Electron. Syst. 25, 5, Article 41 (August 2020), 29 pages. https://doi.org/10.1145/3388141

[1]  Luca Benini,et al.  Regression-based RTL power modeling , 2000, TODE.

[2]  Carlos Carreras,et al.  Power Estimation of Embedded Multiplier Blocks in FPGAs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Sujit Dey,et al.  Register-transfer level estimation techniques for switching activity and power consumption , 1996, Proceedings of International Conference on Computer Aided Design.

[4]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[5]  Farid N. Najm,et al.  Power macromodeling for high level power estimation , 1997, DAC.

[6]  Chalbi Najoua,et al.  Accurate dynamic power model for FPGA based implementations , 2012 .

[7]  Paolo Meloni,et al.  Power and clock gating modelling in coarse grained reconfigurable systems , 2016, Conf. Computing Frontiers.

[8]  Paolo Meloni,et al.  Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures , 2016, J. Electr. Comput. Eng..

[9]  Domenik Helms,et al.  Leakage Models for High-Level Power Estimation , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Ah Chung Tsoi,et al.  Universal Approximation Using Feedforward Neural Networks: A Survey of Some Existing Methods, and Some New Results , 1998, Neural Networks.

[11]  Jean-Christophe Prévotet,et al.  Efficient modelling of FPGA-based IP blocks using neural networks , 2016, 2016 International Symposium on Wireless Communication Systems (ISWCS).

[12]  Marios C. Papaefthymiou,et al.  Incorporation of input glitches into power macromodeling , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[13]  Li Shang,et al.  High-level power modeling of CPLDs and FPGAs , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[14]  Farid N. Najm,et al.  Power modeling for high-level power estimation , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Luigi Raffo,et al.  NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology , 2019, CF.

[16]  Felix Wortmann,et al.  Internet of Things , 2015, Business & Information Systems Engineering.

[17]  Magdy A. Bayoumi,et al.  Probabilistic Analysis of Power-Gating in Network-on-Chip Routers , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  A. Borovyi,et al.  Using Neural Network for the Evaluation of Power Consumption of Instructions Execution , 2008, 2008 IEEE Instrumentation and Measurement Technology Conference.

[19]  L. Benini,et al.  Lookup table power macro-models for behavioral library components , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[20]  Ligang Hou,et al.  Neural network based power estimation on chip specification , 2010, The 3rd International Conference on Information Sciences and Interaction Sciences.

[21]  S. Karsoliya,et al.  Approximating Number of Hidden layer neurons in Multiple Hidden Layer BPNN Architecture , 2012 .

[22]  Chien-Nan Jimmy Liu,et al.  A novel approach for high-level power modeling of sequential circuits using recurrent neural networks , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[23]  Sergio Bampi,et al.  A power-predictive environment for fast and power-aware ASIC-based FIR filter design , 2017, 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI).

[24]  Prithviraj Banerjee,et al.  Macro-models for high-level area and power estimation on FPGAs , 2006, Int. J. Simul. Process. Model..

[25]  Jean-Christophe Prévotet,et al.  Power modeling on FPGA: a neural model for RT-level power estimation , 2018, CF.

[26]  Chaitali Chakrabarti,et al.  Accurate models for estimating area and power of FPGA implementations , 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

[27]  Stephen L. Diamond,et al.  President's Message: Looking Forward , 2003, Computer.

[28]  F. Machado,et al.  Statistical Power Estimation For Register Transfer Level , 2006, Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006..

[29]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .