Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

In this paper we present the design of a continuous time ΣΔ-modulator in a 0.35 μm technology. While using a 6-bit internal quantizer a total of only 15 comparators were implemented. The inherent loop delay is accounted for in the design by using a design strategy based on the Nyquist stability criterion and the vector gain margin. Measurement results show a Peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.

[1]  Raf Roovers,et al.  12-B, 60-MSample/S cascaded folding and interpolating ADC , 1999 .

[2]  C. S. Petrie,et al.  A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[3]  Andreas Wiesbauer,et al.  Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Michiel Steyaert,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001 .

[5]  W. Snelgrove,et al.  Excess loop delay in continuous-time delta-sigma modulators , 1999 .

[6]  Franco Maloberti,et al.  Op-amp swing reduction in sigma-delta modulators , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[7]  R. Roovers,et al.  A 12 b 50 M sample/s cascaded folding and interpolating ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[8]  Pieter Rombouts,et al.  Nyquist criterion based design of continuous time /spl Sigma//spl Delta/ modulators , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[9]  E. Sanchez-Sinencio,et al.  A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[10]  Johan H. Huijsing,et al.  A 1.8-mW CMOS ΣΔ Modulator with Integrated Mixter for A/D Conversion of IF signals , 1999 .

[11]  M. Clara,et al.  A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution , 2004, IEEE Journal of Solid-State Circuits.

[12]  E.J. van der Zwan,et al.  A 10.7-MHz IF-to-baseband /spl Sigma//spl Delta/ A/D conversion system for AM/FM radio receivers , 2000, IEEE Journal of Solid-State Circuits.

[13]  Maurits Ortmanns,et al.  A continuous–time sigma–delta modulator with reduced jitter sensitivity , 2002 .

[14]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[15]  Maurits Ortmanns,et al.  A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[17]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[18]  Nicolas Beilleau,et al.  Design of Continuous-Time Sigma-Delta Modulators with Sine-Shaped Feedback DACs , 2005 .

[19]  E. J. V. D. Zwan,et al.  A 10.7 MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers , 2000 .

[20]  Pieter Rombouts,et al.  A 250-kHz 94-dB double-sampling /spl Sigma//spl Delta/ modulation A/D converter with a modified noise transfer function , 2003 .

[21]  Kwang Young Kim,et al.  A 10-b, 100-MS/s CMOS A/D converter , 1997 .

[22]  Pieter Rombouts,et al.  Controlled behaviour of STF in CT ΣΔ modulators , 2005 .

[23]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[24]  Richard Kielbasa,et al.  Synthesis and Analysis of Sigma-Delta Modulators Employing Continuous-Time Filters , 2000 .

[25]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[26]  R. V. Veldhoven.  A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[27]  Shanthi Pavan,et al.  Fundamental Limitations of Continuous-Time Delta–Sigma Modulators Due to Clock Jitter , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[28]  Kenneth W. Martin,et al.  High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[29]  Pieter Rombouts,et al.  Efficient Multibit Quantization in Continuous-Time $\Sigma \Delta$ Modulators , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.