Low-Power Instruction Address Bus Coding with Xor-bits Architecture
暂无分享,去创建一个
[1] Masahiro Fujita,et al. Irredundant address bus encoding techniques based on adaptive codebooks for low power , 2003, ASP-DAC '03.
[2] Sujit Dey,et al. High-level crosstalk defect Simulation methodology for system-on-chip interconnects , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Mircea R. Stan,et al. Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[4] Nikil D. Dutt,et al. Adaptive low-power address encoding techniques using self-organizing lists , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[5] Naresh R. Shanbhag,et al. A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[6] Mary Jane Irwin,et al. Some issues in gray code addressing , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.
[7] Massoud Pedram,et al. ALBORZ: Address Level Bus Power Optimization , 2002, Proceedings International Symposium on Quality Electronic Design.
[8] Tomás Lang,et al. Working-zone encoding for reducing the energy in microprocessor address buses , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[9] Chi-Ying Tsui,et al. Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.
[10] Ali Afzali-Kusha,et al. A very high performance address BUS encoder , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[11] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[12] Luca Benini,et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.
[13] V. Kamakoti,et al. Dynamic coding technique for low-power data bus , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..
[14] Tughrul Arslan,et al. Bus encoding architecture for low-power implementation of an AMBA-based SoC platform , 2002 .
[15] Kiyoung Choi,et al. Narrow bus encoding for low-power DSP systems , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[16] Massoud Pedram,et al. EZ encoding: a class of irredundant low power codes for data address and multiplexed address buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[17] Kiyoung Choi,et al. Narrow bus encoding for low power systems , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).
[18] Luca Benini,et al. Address bus encoding techniques for system-level power optimization , 1998, Proceedings Design, Automation and Test in Europe.
[19] Cristina Silvano,et al. Power optimization of system-level address buses based on software profiling , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).
[20] Massoud Pedram,et al. Irredundant address bus encoding for low power , 2001, ISLPED '01.
[21] Masahiro Fujita,et al. Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications , 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..