Hardware Efficient Architecture for Element-Based Lattice Reduction Aided K-Best Detector for MIMO Systems

Multiple-Input Multiple-Output (MIMO) systems are characterised by increased capacity and improved performance compared to the single-input single-output (SISO) systems. One of the main challenge in the design of MIMO systems is the detection of the transmitted signals due to the interference caused by the multiple simultaneously transmitted symbols from the multiple transmit antennas. Several detection techniques have been proposed in the literature in order to reduce the detection complexity, while maintaining the required quality of service. Among these low-complexity techniques is the Lattice Reduction (LR), which can provide good performance and significantly lower complexity compared to Maximum Likelihood (ML) detector. In this paper we propose to use the so-called Element-based Lattice Reduction (ELR) combined with K-Best detector for the sake of attaining a better Bit Error Ratio (BER) performance and lower complexity than the conventional Lenstra, Lanstra, and Lovasz (LLL) LR-aided detection. Additionally, we propose a hardware implementation for the ELR-aided K-Best detector for a MIMO system equipped with four transmit and four receive antennas. The ELR-aided K-Best detector requires an extra 18% increase in power consumption and an extra 20% in area overhead compared to a regular K-Best detector dispensing with ELR, where this increase in the hardware requirements is needed in order to achieve a 2 dB performance improvement at a bit error rate of 10−5.