FPGA Implementation of the Gradient Adaptive Lattice Filter Structure for Feature Extraction

In this paper evaluation issues of an FPGA implementation of the feature extraction gradient adaptive lattice (GAL) filter are presented. Two different hardware architectures for implementation in the Virtex family of FPGA devices were proposed, namely a single GAL section coprocessor of Virtex PowerPC., and a pipeline architecture. Both of them show significantly higher performance comparing to their software implementation.

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