Automatic monitoring for interactive performance and power reduction

The goal of interactive applications is to respond to user events under human perception bounds. However, existing operating systems do not have a way of dynamically evaluating the quality of the user experience. In this research we describe a mechanism that, by monitoring the communication between the tasks in the system, can automatically isolate execution episodes that directly impact the user. We use this technique to quantify the impact of multiprocessing on the response times of interactive applications and it forms the basis of a power management scheme that works by reducing the performance level of the processor when peak performance is unnecessary. We find that using two processors instead of one can improve the perceptible response-times of interactive applications by 20% to 30%. Our performance-setting algorithm for processors that support dynamic voltage scaling improves on previous algorithms in that it works equally well with irregular and multiprogrammed workloads and has the ability to ensure that interactive performance is within user specified parameters. Our simulations indicate that as a result of our algorithm, the energy used by the processor can be reduced by 20%–75% without a significant impact on the user experience.

[1]  Krisztián Flautner,et al.  Automatic Performance Setting for Dynamic Voltage Scaling , 2001, MobiCom '01.

[2]  Susan J. Eggers,et al.  An analysis of database workload performance on simultaneous multithreaded processors , 1998, ISCA.

[3]  Trevor Pering,et al.  Dynamic Voltage Scaling and the Design of a Low-Power Microprocessor System , 1998 .

[4]  R. Brodersen,et al.  Voltage Scheduling in the lpARM Microprocessor System , 2000 .

[5]  Michael D. Smith,et al.  The measured performance of personal computer operating systems , 1995, SOSP.

[6]  Trevor Mudge,et al.  Thread-level parallelism and interactive performance of desktop applications , 2000, SIGP.

[7]  Michael Culbert Low power hardware for a high performance PDA , 1994, Proceedings of COMPCON '94.

[8]  Allen Newell,et al.  The psychology of human-computer interaction , 1983 .

[9]  Philip Levis,et al.  Policies for dynamic clock scheduling , 2000, OSDI.

[10]  Joel Emer,et al.  Proceedings of the 50th Annual International Symposium on Computer Architecture , 2000, International Symposium on Computer Architecture.

[11]  José C. Monteiro,et al.  Scheduling techniques to enable power management , 1996, DAC '96.

[12]  Scott Shenker,et al.  Scheduling for reduced CPU energy , 1994, OSDI '94.

[13]  Trevor Mudge,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001 .

[14]  Carl Staelin,et al.  Idleness is Not Sloth , 1995, USENIX.

[15]  Alan Jay Smith,et al.  Reducing processor power consumption by improving processor time management in a single-user operating system , 1996, MobiCom '96.

[16]  Hal Wasserman,et al.  Comparing algorithm for dynamic speed-setting of a low-power CPU , 1995, MobiCom '95.

[17]  Michael S. Hsiao,et al.  Compiler-Directed Dynamic Frequency and Voltage Scheduling , 2000, PACS.

[18]  Giovanni De Micheli,et al.  Software controlled power management , 1999, CODES '99.

[19]  Marvin Theimer,et al.  Using threads in interactive systems: a case study , 1993, SOSP '93.

[20]  James P. Held,et al.  A comparison of Windows driver model latency performance on Windows NT and Windows 98 , 1999, OSDI '99.

[21]  E AndersonThomas,et al.  Execution characteristics of desktop applications on Windows NT , 1998 .

[22]  Keith Diefendorff Compaq chooses smt for alpha: simultaneous multithreading exploits instruction- and thread-level par , 1999 .

[23]  Luca Benini,et al.  Monitoring system activity for OS-directed dynamic power management , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[24]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[25]  Hiroto Yasuura,et al.  Real-time task scheduling for a variable voltage processor , 1999, Proceedings 12th International Symposium on System Synthesis.

[26]  Kiyoung Choi,et al.  Power conscious fixed priority scheduling for hard real-time systems , 1999, DAC '99.

[27]  Zheng Wang,et al.  Using latency to evaluate interactive system performance , 1996, OSDI '96.

[28]  Thomas D. Burd,et al.  Voltage scheduling in the IpARM microprocessor system , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[29]  Helen Custer,et al.  Inside Windows NT , 1992 .

[30]  Bil Lewis,et al.  Multithreaded Programming With PThreads , 1997 .

[31]  Luiz André Barroso,et al.  Piranha: a scalable architecture based on single-chip multiprocessing , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[32]  J. Flinn,et al.  Energy-aware adaptation for mobile applications , 1999, SOSP.

[33]  David A. Solomon,et al.  Inside windows nt second edition , 1998 .

[34]  Dan R. Olsen,et al.  Developing user interfaces , 1998 .

[35]  Thomas D. Burd,et al.  The simulation and evaluation of dynamic voltage scaling algorithms , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[36]  Kunle Olukotun,et al.  Considerations in the Design of Hydra: A Multiprocessor-on-a-Chip Microarchitecture , 1998 .

[37]  Yann-Hang Lee,et al.  Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems , 2000, Proceedings Sixth IEEE Real-Time Technology and Applications Symposium. RTAS 2000.

[38]  Richard A. Uhlig,et al.  Thread Level Parallelism of Desktop Applications , 2000, ASPLOS 2000.