An Efficient VLSI Architecture for MPEG-4 Motion Estimation

A highly parallel and pipelined VLSI architecture for MPEG-4 motion estimation is proposed in this paper, searching for the best match to the reference block by full search block matching algorithm to enhance the video quality. It possesses the characteristics of low embedded memory, low clock rate with high accuracy, aiming at both mobile and high-definition applications. The proposed architecture has been prototyped based on FUJITSU CE66 cells.