Improved SVPWM vector selection approaches in OVM region to reduce common-mode voltage for three-level neutral point clamped inverter

Abstract Multilevel inverters (MLIs) have an essential portion in industrial applications. Eventhough there are various elementary developments in MLI and its pulse width modulation (PWM) control strategies, unfortunately those strategies are least bothered about the common mode voltage (CMV). The CMV appears at the neutral point of the motor’s star connected stator windings with respect to the source ground. This study proposes PWM schemes for three level diode clamped multilevel inverter (DC-MLI) which use an unpretentious switching sequence to determine the triangle for maximum output voltage and minimum CMV in entire modulation range. Here two types of approaches are proposed: (i) Partial elimination SVPWM (PE-SVPWM) and (ii) Full elimination (FE-SVPWM). The proposed strategies suggest switching selection by using the control degree of freedom available in SVPWM without affecting the inverter output voltage. As a result, CMV reduction and elimination with maximum output voltage and better THD is achieved. The proposed PWM approaches can be extended for any number of levels. The theoretical study, the MATLAB/Simulink software based computer simulation and Field Programmable Gate Array (FPGA) SPARTAN-III-3AN-XC3S400 processor supported hardware corroboration have shown the superiority of the proposed technique over the existing SVPWM schemes.

[1]  José R. Rodríguez,et al.  A Survey on Neutral-Point-Clamped Inverters , 2010, IEEE Transactions on Industrial Electronics.

[2]  Frede Blaabjerg,et al.  Common-mode voltage reduction in a motor drive system with a power factor correction , 2012 .

[3]  Poh Chiang Loh,et al.  Reduced common-mode modulation strategies for cascaded multilevel inverters , 2003 .

[4]  Jorge Pontt,et al.  A new modulation method to reduce common-mode voltages in multilevel inverters , 2004, IEEE Transactions on Industrial Electronics.

[5]  Shaoan Dai,et al.  A multilevel inverter approach providing DC-link balancing, ride-through enhancement, and common-mode voltage elimination , 2002, IEEE Trans. Ind. Electron..

[6]  Abdul Rahiman Beig.  Synchronized SVPWM Algorithm for the Overmodulation Region of a Low Switching Frequency Medium-Voltage Three-Level VSI , 2012, IEEE Transactions on Industrial Electronics.

[7]  F.C. Lee,et al.  Common-Mode Noise Reduction for Power Factor Correction Circuit With Parasitic Capacitance Cancellation , 2007, IEEE Transactions on Electromagnetic Compatibility.

[8]  A.K. Gupta,et al.  A Space Vector Modulation Scheme to Reduce Common Mode Voltage for Cascaded Multilevel Inverters , 2007, IEEE Transactions on Power Electronics.

[9]  M. Renge,et al.  Five-Level Diode Clamped Inverter to EliminateCommon Mode Voltage and Reduce $dv/dt$ inMedium Voltage Rating Induction Motor Drives , 2008, IEEE Transactions on Power Electronics.

[10]  Bimal K. Bose,et al.  Space vector pulse width modulation of three-level inverter extending operation into overmodulation region , 2003 .

[11]  K. Lee,et al.  Quantitative Power Quality and Characteristic Analysis of Multilevel Pulsewidth-Modulation Methods for Three-Level Neutral-Point-Clamped Medium-Voltage Industrial Drives , 2012, IEEE Transactions on Industry Applications.

[12]  K.R.M.N. Ratnayake,et al.  A novel PWM scheme to eliminate common-mode voltage in three-level voltage source inverter , 1998, PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference (Cat. No.98CH36196).

[13]  Yves Gemeinder,et al.  Calculation of bearing and common-mode voltages for the prediction of bearing failures caused by EDM currents , 2011, 8th IEEE Symposium on Diagnostics for Electrical Machines, Power Electronics & Drives.

[14]  Annette Muetze,et al.  Practical Rules for Assessment of Inverter-Induced Bearing Currents in Inverter-Fed AC Motors up to 500 kW , 2007, IEEE Transactions on Industrial Electronics.

[15]  Brayima Dakyo,et al.  A new active common-mode voltage elimination method for three-Level Neutral-Point Clamped inverters , 2014, IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society.

[16]  K. Gopakumar,et al.  Multilevel inverters for low-power application , 2011 .

[17]  Zhengming Zhao,et al.  Hybrid Selective Harmonic Elimination PWM for Common-Mode Voltage Reduction in Three-Level Neutral-Point-Clamped Inverters for Variable Speed Induction Drives , 2012, IEEE Transactions on Power Electronics.

[18]  Hojoon Shin,et al.  Low-Common Mode Voltage H-Bridge Converter with Additional Switch Legs , 2013, IEEE Transactions on Power Electronics.

[19]  S. Paramasivam,et al.  Dynamically Reconfigurable PWM Controller for Three-Phase Voltage-Source Inverters , 2011, IEEE Transactions on Power Electronics.

[20]  K. Gopakumar,et al.  Three-Level Inverter Scheme With Common Mode Voltage Elimination and DC Link Capacitor Voltage Balancing for an Open-End Winding Induction Motor Drive , 2006, IEEE Transactions on Power Electronics.

[21]  Seung-Ki Sul,et al.  A new PWM strategy for common mode voltage reduction in neutral-point clamped inverter-fed AC motor drives , 2000, Conference Record of the 2000 IEEE Industry Applications Conference. Thirty-Fifth IAS Annual Meeting and World Conference on Industrial Applications of Electrical Energy (Cat. No.00CH37129).

[22]  Philippe Baudesson,et al.  A New Carrier-Based PWM Providing Common-Mode-Current Reduction and DC-Bus Balancing for Three-Level Inverters , 2007, IEEE Transactions on Industrial Electronics.

[23]  Bin Wu,et al.  An Integrated AC Choke Design for Common-Mode Current Suppression in Neutral-Connected Power Converter Systems , 2012, IEEE Transactions on Power Electronics.

[24]  A. Muetze,et al.  Simplified Design of Common-Mode Chokes for Reduction of Motor Ground Currents in Inverter Drives , 2006, IEEE Transactions on Industry Applications.

[25]  S. Jeevananthan,et al.  FPGA based practical implementation of NPC-MLI with SVPWM for an autonomous operation PV system with capacitor balancing , 2014 .

[26]  Seung-Ki Sul,et al.  A new active common-mode EMI filter for PWM inverter , 2003 .

[27]  Hiralal M. Suryawanshi,et al.  Three-Dimensional Space-Vector Modulation to Reduce Common-Mode Voltage for Multilevel Inverter , 2010, IEEE Transactions on Industrial Electronics.

[28]  M. J. Duran,et al.  Reduction of Common-Mode Voltage in Five-Phase Induction Motor Drives Using Predictive Control Techniques , 2012, IEEE Transactions on Industry Applications.

[29]  R.M. Cuzner,et al.  Implementation of a Four-Pole Dead-Time-Compensated Neutral-Point-Clamped Three-Phase Inverter With Low Common-Mode Voltage Output , 2009, IEEE Transactions on Industry Applications.