Analysis of Noise Coupling and Timing Error in Silicon Bridge Application

Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a single package. It also provides a low-impedance path for the power delivery between two or more SoCs. However, a congested dense signal routing inside the silicon bridge makes the timing error worse. The switching noise on the power rail also increases the timing error of the interfaces. We investigated all possible sources of self-generated and coupled noise inside silicon bridge and analyzed the impact on the timing error.

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