Design and analysis of different types SRAM cell topologies

In this paper, we design different type of SRAM cells. This paper compares the performance of five SRAM cell topologies, which include the conventional 6T, 7T, 8T, 9T and the 10T SRAM cell implementations. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. In 10T SRAM cell implementation results, reduced leakage power and leakage current by 36% and 64% respectively, the read stability is increased by 13% over conventional 6T, 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. The aim of this paper is to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.

[1]  Shilpi Birla,et al.  Static Noise Margin Analysis of Various SRAM Topologies , 2011 .

[2]  Shilpi Birla,et al.  ANALYSIS OF THE DATA STABILITY AND LEAKAGE POWER IN THE VARIOUS SRAM CELLS TOPOLOGIES , 2010 .

[3]  Guru Shamanna,et al.  Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness , 2010, 23rd IEEE International SOC Conference.

[4]  David Blaauw,et al.  A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[5]  Doris Schmitt-Landsiedel,et al.  Countermeasures against NBTI degradation on 6T-SRAM cells , 2011 .

[6]  T. Mudge,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.

[7]  Kaushik Roy,et al.  A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Masahiro Nomura,et al.  A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[9]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  Kawaguchi Hiroshi,et al.  7T SRAM Enabling Low-Energy Simultaneous Block Copy , 2010 .

[11]  M. Omair Ahmad,et al.  An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[12]  K. Roy,et al.  DRG-cache: a data retention gated-ground cache for low power , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[13]  Yong-Gee Ng,et al.  A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology , 2009, IEEE Journal of Solid-State Circuits.